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16 Mbit LPC Serial Flash
A Microchip Technology Company
SST49LF016C
Data Sheet
Registers
There are five types of registers available on the SST49LF016C, the multi-byte Read/Write configura-
tion registers (for Firmware Memory cycle), General Purpose Inputs registers, Block Locking registers,
Security ID register, and the JEDEC ID registers. These registers appear at their respective address
location in the 4 GByte system memory map. Unused register locations will read as 00H. Any attempt
to read or write any register during an internal Write operation will be ignored.
Read or write access to the register during an internal Program/Erase operation will be completed as
follows:
?
?
Multi-byte Read/Write Configuration registers, General Purpose Inputs register, and Block
Locking registers can be accessed normally
Security ID register and the JEDEC ID registers can not be accessed (reading these reg-
isters will return unused register data 00H).
Multi-Byte Read/Write Configuration Registers (Firmware Memory Cycle)
The multi-byte read/write configuration (MBR) registers are four 8-bit read-only registers located at
addresses FFBC0005-FFBC0008 for boot configured device (see Table 13). These registers are
accessible using Firmware Memory Read cycle only. These registers contain information about multi-
byte read and write access sizes that will be accepted for Firmware Memory multi-byte Read com-
mands. The registers are not available in AAI mode.
In case of multi-byte Firmware Memory register reads, the device will return register data for the
addressed register until the command finishes, or is aborted.
General Purpose Inputs Register
The General Purpose Inputs register (GPI_REG) passes the state of GPI[4:0] pins on the
SST49LF016C. It is recommended that the GPI[4:0] pins be in the desired state before LFRAME# is
brought low for the beginning of the bus cycle, and remain in that state until the end of the cycle. There
is no default value since this is a pass-through register. The GPI_REG register for the boot device
appears at FFBC0100H in the 4 GByte system memory map, and will appear elsewhere if the device is
not the boot device (see Table 12). This register is not available to be read when the device is in an
Erase/Program operation. In case of multi-byte Firmware Memory cycle register reads, the device will
return register data for the addressed register until the command finishes, or is aborted.
Table 12: General Purpose Register
Default
Register
GPI_REG
Register Address 1
FFBC 0100H
Value
N/A
Access
R
T12.0 25029
1. Address shown in this column is for boot device only. Address locations should appear elsewhere in the 4 GByte system
memory map depending on ID strapping values on ID[3:0] pins when multiple LPC memory devices are used in a sys-
tem.
?2011 Silicon Storage Technology, Inc.
21
DS25029A
06/11
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